Architectures for computer vision: from algorithm to chip with Verilog

This book provides comprehensive coverage of 3D vision systems, from vision models and state-of-the-art algorithms to their hardware architectures for implementation on DSPs, FPGA and ASIC chips, and GPUs. It aims to fill the gaps between computer vision algorithms and real-time digital circuit implementations, especially with Verilog HDL design. The organization of this book is vision and hardware module directed, based on Verilog vision modules, 3D vision modules, parallel vision architectures, and Verilog designs for the stereo matching system with various parallel architectures. Provides Verilog vision simulators, tailored to the design and testing of general vision chips Bridges the differences between C/C++ and HDL to encompass both software realization and chip implementation; includes numerous examples that realize vision algorithms and general vision processing in HDL Unique in providing an organized and complete overview of how a real-time 3D vision system-on-chip can be designed Focuses on the digital VLSI aspects and implementation of digital signal processing tasks on hardware platforms such as ASICs and FPGAs for 3D vision systems, which have not been comprehensively covered in one single book Provides a timely view of the pervasive use of vision systems and the challenges of fusing information from different vision modules Accompanying website includes software and HDL code packages to enhance further learning and develop advanced systems A solution set and lecture slides are provided on the book's companion website The book is aimed at graduate students and researchers in computer vision and embedded systems, as well as chip and FPGA designers. Senior undergraduate students specializing in VLSI design or computer vision will also find the book to be helpful in understanding advanced applications.

Architectures for Computer Vision -- Contents -- About the Author -- Preface -- Part One Verilog HDL -- 1 Introduction -- 1.1 Computer Architectures for Vision -- 1.2 Algorithms for Computer Vision -- 1.3 Computing Devices for Vision -- 1.4 Design Flow for Vision Architectures -- Problems -- References -- 2 Verilog HDL, Communication, and Control -- 2.1 The Verilog System -- 2.2 Hello, World! -- 2.3 Modules and Ports -- 2.4 UUT and TB -- 2.5 Data Types and Operations -- 2.6 Assignments -- 2.7 Structural-Behavioral Design Elements -- 2.8 Tasks and Functions -- 2.9 Syntax Summary -- 2.10 Simulation-Synthesis -- 2.11 Verilog System Tasks and Functions -- 2.12 Converting Vision Algorithms into Verilog HDL Codes -- 2.13 Design Method for Vision Architecture -- 2.14 Communication by Name Reference -- 2.15 Synchronous Port Communication -- 2.16 Asynchronous Port Communication -- 2.17 Packing and Unpacking -- 2.18 Module Control -- 2.19 Procedural Block Control -- Problems -- References -- 3 Processor, Memory, and Array -- 3.1 Image Processing System -- 3.2 Taxonomy of Algorithms and Architectures -- 3.3 Neighborhood Processor -- 3.4 BPBP Processor -- 3.5 DP Processor -- 3.6 Forward and B…