Computer arithmetic

Computer Arithmetic Volume III is a compilation of key papers in computer arithmetic on floating-point arithmetic and design. The intent is to show progress, evolution, and novelty in the area of floating-point arithmetic. This field has made extraordinary progress since the initial software routines on mainframe computers have evolved into hardware implementations in processors spanning a wide range of performance. Nevertheless, these papers pave the way to the understanding of modern day processors design where computer arithmetic are supported by floating-point units. The goal of Volume III is to collect the defining document for floating-point arithmetic and many of the key papers on the implementation of both binary and decimal floating-point arithmetic into a single volume. Although fewer than forty papers are included, their reference lists will direct the interested reader to other excellent work that could not be included here. Volume III is specifically oriented to the needs of designers and users of both general-purpose computers and special-purpose digital processors. The book should also be useful to systems engineers, computer architects, and logic designers. It is also intended to serve as a primary text for a course on floating-point arithmetic, as well as a supplementary text for courses in digital arithmetic and high-speed signal processing.

Pt. I. Overview. 1. IEEE standard for floating-point arithmetic -- pt. II. Floating-point addition. 2. Delay-optimized implementation of IEEE floating-point addition / P. M. Seidel and G. Even -- 3. Using the reverse-carry approach for double datapath floating-point addition / J. D. Bruguera and T. Lang -- 4. Reduced latency IEEE floating-point standard adder architectures / A. Beaumont-Smith ... [et al.] -- 5. Leading-zero anticipatory logic for high-speed floating-point addition / H. Suzuki ... [et al.] -- 6. Leading zero anticipation and detection -- A comparison of methods / M. Schmookler and K. Nowka -- 7. S/370 sign-magnitude floating-point adder / S. Vassiliadis, D. S. Lemon and M. Putrino -- pt. III. Floating-point multiplication. 8. A quadruple precision and dual double precision floating-point multiplier / A. Akkas and M. J. Schulte -- 9. A dual mode IEEE multiplier / G. Even, S. M. Mueller and P. M. Seidel -- ^

10. 167 MHz radix-4 floating-point multiplier / R. K. Yu and G. B. Zyner -- pt. IV. Rounding. 11. Rounding algorithms for IEEE multipliers / M. R. Santoro, G. Bewick and M. A. Horowitz -- 12. "Systematic IEEE rounding method for high-speed floating-point multipl…