Computer arithmetic: volume III

Pt. I. Overview. 1. IEEE standard for floating-point arithmetic -- pt. II. Floating-point addition. 2. Delay-optimized implementation of IEEE floating-point addition / P.M. Seidel and G. Even -- 3. Using the reverse-carry approach for double datapath floating-point addition / J.D. Bruguera and T. Lang -- 4. Reduced latency IEEE floating-point standard adder architectures / A. Beaumont-Smith [und weitere] -- 5. Leading-zero anticipatory logic for high-speed floating-point addition / H. Suzuki [und weitere] -- 6. Leading zero anticipation and detection - A comparison of methods / M. Schmookler and K. Nowka -- 7. S/370 sign-magnitude floating-point adder / S. Vassiliadis, D.S. Lemon and M. Putrino -- pt. III. Floating-point multiplication. 8. A quadruple precision and dual double precision floating-point multiplier / A. Akkas and M.J. Schulte -- 9. A dual mode IEEE multiplier / G. Even, S.M. Mueller and P.M. Seidel -- 10. 167 MHz radix-4 floating-point multiplier / R.K. Yu and G.B. Zyner -- pt. IV. Rounding. 11. Rounding algorithms for IEEE multipliers / M.R. Santoro, G. Bewick and M.A. Horowitz -- 12. "Systematic IEEE rounding method for high-speed floating-point multipliers / N.T. Quach, N. Takagi, and M.J. Flynn -- 13. A comparison of three rounding algorithms for IEEE floating-point multiplication / G. Even and P.M. Seidel -- 14. Prenormalization rounding in IEEE floating-point operations using a flagged prefix adder / N. Burgess -- pt. V. Fused multiply add. 15. Design of the IBM RISC system/6000 floating-point execution unit / R.K. Montoye, E. Hokenek and S.L. Runyon -- 16. A 17 x 69 bit multiply and add unit with redundant binary feedback and single cycle latency / W.S. Briggs and D. Matula -- 17. Comparison of single- and dual-pass multiply-add fused floating-point units / R. Jessani and M. Putrino -- 18. Floating-point fused multiply-add with reduced latency / T. Lang and J.D. Bruguera -- 19. Floating-point fused multiply-add architectures / E. Quinnell, E.E. Swartzlander, Jr. and C. Lemonds -- pt. VI. Floating-point division. 20. Floating-point division and square root algorithms and implementation in the AMD-K7 microprocessor / S.F. Oberman -- 21. High performance floating-point unit with 116 bit wide divider / G. Gerwig [und weitere] -- 22. High-speed double-precision computation of reciprocal, division, square root, and inverse square root / J.A. Pineiro and J.D. Bruguera -- 23. 167 MHz radix-8 floating-point divide and square root using overlapped radix-2 stages / J. Prabhu and G. Zyner -- 24. Division algorithms and implementations / S.F. Oberman and M.J. Flynn -- 25. Faithful interpolation in reciprocal tables / D. Das Sarma and D.W. Matula -- pt. VII. Elementary functions. 26. Computation of elementary functions on the IBM RISC system/6000 processor / P.W. Markstein -- 27. Accurate and monotone approximations of some transcendental functions / W. Ferguson and T. Brightman -- 28. The K5 transcendental functions / T. Lynch [und weitere] -- 29. Hardware designs for exactly rounded elementary functions / M.J. Schulte and E.E. Swartzlander, Jr. -- 30. Toward correctly rounded transcendentals / V. Lefevre, J.-M. Muller and A. Tisserand -- 31. Reciprocation, square root, inverse square root and some elementary functions using small multipliers / M. Ercegovac [und weitere] -- 32. Multipartite table methods / F. Dinechin and A. Tisserand -- pt .VIII. Decimal floating-point arithmetic. 33. A decimal floating-point specification / M.F. Cowlishaw [und weitere] -- 34. Decimal floating-point: Algorism for computers / M.F. Cowlishaw -- 35. A software implementation of the IEEE 754R decimal floating-point arithmetic using the binary encoded format / M. Cornea [und weitere] -- 36. Decimal floating-point multiplication, / M.A. Erle, B.J. Hickmann and M.J. Schulte -- 37. "A survey of hardware designs for decimal arithmetic / L.-K. Wang [und weitere]

Computer Arithmetic Volume III is a compilation of key papers in computer arithmetic on floating-point arithmetic and design. The intent is to show progress, evolution, and novelty in the area of floating-point arithmetic. This field has made extraordinary progress since the initial software routines on mainframe computers have evolved into hardware implementations in processors spanning a wide range of performance. Nevertheless, these papers pave the way to the understanding of modern day processors design where computer arithmetic are supported by floating-point units. The goal of Volume III is to collect the defining document for floating-point arithmetic and many of the key papers on the implementation of both binary and decimal floating-point arithmetic into a single volume. Although fewer than forty papers are included, their reference lists will direct the interested reader to other excellent work that could not be included here. Volume III is specifically oriented to the needs of designers and users of both general-purpose computers and special-purpose digital processors. The book should also be useful to systems engineers, computer architects, and logic designers. It is also intended to serve as a primary text for a course on floating-point arithmetic, as well as a supplementary text for courses in digital arithmetic and high-speed signal processing