Computer Organization: Basic Processor Structure

Cover -- Half title -- Title -- Copyrights -- Dedication -- Contents -- Introduction and Remarks -- Chapter 1 Overview -- 1.1 HIGH-LEVEL, ASSEMBLY, AND MACHINE LANGUAGES -- 1.1.1 High-Level Languages -- 1.1.2 Machine Language -- 1.1.3 Assembly Language -- 1.2 COMPILERS AND ASSEMBLY LANGUAGE -- 1.2.1 Assembly Language Translation -- 1.2.2 The Translation Process -- 1.3 THE ASSEMBLER AND OBJECT CODE -- 1.3.1 External References -- 1.3.2 Compiler versus Assembler -- 1.4 THE LINKER AND EXECUTABLE CODE -- 1.4.1 Resolving External References -- 1.4.2 Searching Libraries -- 1.4.3 Relocation -- 1.5 THE LOADER -- 1.5.1 Processes and Workspaces -- 1.5.2 Initializing Registers -- 1.6 SUMMARY OF THE TRANSLATION PROCESS -- 1.7 THE PROCESSOR -- 1.7.1 Processor Behavior -- 1.7.2 Processor Structure -- 1.7.2.1 The Data Path, Registers, and Compu- tational Units -- 1.7.2.2 Control Circuitry -- 1.8 DIGITAL CIRCUITRY -- 1.9 SUMMARY -- 1.10 EXERCISES -- Chapter 2 Number and Logic Systems -- 2.1 NUMBERS -- 2.1.1 Hexadecimal Numbers -- 2.1.2 Adding Binary Numbers -- 2.1.3 Representing Negative Integers -- 2.2 BOOLEAN ALGEBRA -- 2.2.1 Boolean Functions -- 2.2.2 Boolean Expressions and Truth Tables -- 2.2.3 Don't Care Conditions -- 2.2.4 Boolean Simpli cation Using Identities -- 2.2.4.1 Boolean Identities -- 2.2.4.2 DeMorgan's Law -- 2.2.4.3 Simplifying the XOR Function -- 2.2.4.4 Example Simpli cation Using Identities -- 2.2.5 Boolean Simpli cation Using Karnaugh-Maps -- 2.2.5.1 K-Map for Functions of Two Variables -- 2.2.5.2 K-Maps for Functions of Three Variables -- 2.2.5.3 K-Maps for Functions of Four Variables -- 2.2.5.4 Don't Care Conditions in Karnaugh- Maps -- 2.2.5.5 K-Maps for Functions of More than Four Variables -- 2.3 SUMMARY -- 2.4 EXERCISES -- Chapter 3 Digital Circuitry -- 3.1 COMBINATIONAL CIRCUITS -- 3.1.1 Designing with Logical Gates.

3.1.2 Common Combinational Circuits -- 3.1.2.1 The Decoder -- 3.1.2.2 The Encoder -- 3.1.2.3 The Multiplexer -- 3.1.2.4 MUX Composition -- 3.1.2.5 The Adder -- 3.1.2.6 The Ripple-Carry Adder -- 3.2 SEQUENTIAL CIRCUITS -- 3.2.1 The Clock -- 3.2.2 Storage Devices -- 3.2.2.1 The D-Type Storage Devices -- 3.2.2.2 The D-Latch -- 3.2.2.3 The D-Flip-Flop -- 3.2.2.4 The J-K- Storage Device -- 3.2.2.5 Flip-Flops with Extra Pins -- 3.2.3 Sequential Design -- 3.2.3.1 The FSM and State Diagrams -- 3.2.3.2 The FSM and the State Transition Table -- 3.2.3.3 State Diagrams and Transition Tables: Building One Representation from the Other -- 3.2.3.4 Moore versus Mealy Machines -- 3.2.3.5 Implementing a Sequential Design -- 3.2.4 Sequential Circuit Analysis -- 3.2.5 Common Sequential Circuits -- 3.2.5.1 The Parallel-Load Register -- 3.2.5.2 The Shift Register -- 3.2.5.3 The Counter -- 3.2.5.4 The Standard Register -- 3.3 SUMMARY -- 3.4 EXERCISES -- Chapter 4 Devices and the Bus -- 4.1 MEMORY -- 4.1.1 Memory Operation -- 4.1.2 Memory Types: ROM and RAM -- 4.1.3 Memory Composition -- 4.1.3.1 Horizontal Composition -- 4.1.3.2 Vertical Composition -- 4.1.4 Internal Memory Structure -- 4.1.5 RAM Types -- 4.1.6 ROM Types -- 4.1.7 Word and Byte Addressing -- 4.1.8 Machine Byte Order -- 4.2 PERIPHERAL DEVICES -- 4.2.1 Peripheral Device Types -- 4.2.2 Device Polling -- 4.2.3 Interrupts -- 4.3 THE CPU -- 4.4 BUS COMMUNICATION -- 4.4.1 Bus Structure -- 4.4.2 Bus Addressing -- 4.4.3 Bus Addressing Example -- 4.5 SUMMARY -- 4.6 EXERCISES -- Chapter 5 The Register Transfer Language Level -- 5.1 MICRO-INSTRUCTIONS AS CIRCUITS -- 5.1.1 RTL Design -- 5.1.2 A Larger Example -- 5.1.3 RTL Analysis -- 5.1.4 Transforming a Structural Description into a Be- havioral Description -- 5.1.5 Problems with Reverse Engineering -- 5.2 COMMON PROCESSOR MICRO-INSTRUCTIONS.

5.2.1 RTL Descriptions of Combinational Circuits -- 5.2.2 RTL Descriptions of Sequential Circuits -- 5.2.3 Processor Micro-Operations -- 5.2.3.1 Arithmetic Micro-Operations -- 5.2.3.2 Logic Micro-Operations -- 5.2.3.3 Shift Micro-Operations -- 5.2.3.4 Memory Access Micro-Operations -- 5.3 ALGORITHMIC MACHINES -- 5.3.1 The Teapot Example -- 5.3.2 Generating a Flowchart, and the Role of the Se- quencer -- 5.3.3 Generating RTL from the Flowchart -- 5.4 RTL AND VERILOG -- 5.5 SUMMARY -- 5.6 EXERCISES -- Chapter 6 Common Computer Architectures -- 6.1 INSTRUCTION SET ARCHITECTURE -- 6.1.1 Data Transfer -- 6.1.1.1 Register-to-Register Transfer -- 6.1.1.2 Register-to-Memory Transfer -- 6.1.1.3 Memory-to-Register Transfer -- 6.1.1.4 Device Transfer -- 6.1.2 Data Manipulation Instructions -- 6.1.2.1 Common Data-Types -- 6.1.2.2 The Integer Data-Type -- 6.1.2.3 The Real Data-Type -- 6.1.2.4 The Boolean Data-Type -- 6.1.2.5 The Character Data-Type -- 6.1.2.6 Binary Coded Decimal -- 6.1.2.7 Data Manipulation Operation Types -- 6.1.2.8 Arithmetic Operations -- 6.1.2.9 Logic Operations -- 6.1.2.10 Shift Operations -- 6.1.3 Control Operations -- 6.1.3.1 Unconditional Branches -- 6.1.3.2 Conditional Branches -- 6.1.3.3 Machine Reset Instructions -- 6.1.3.4 Context Manipulation Instructions -- 6.2 INSTRUCTION FORMAT -- 6.3 ADDRESSING MODES -- 6.3.1 Direct Mode -- 6.3.2 Indirect Mode -- 6.3.3 Register Direct Mode -- 6.3.4 Register Indirect Mode -- 6.3.5 Immediate Mode -- 6.3.6 Implicit Mode -- 6.3.7 Relative Mode -- 6.3.8 Indexed Mode -- 6.3.9 Addressing in Machine Language -- 6.4 ALTERNATE MACHINE ARCHITECTURES -- 6.4.1 The Register Machine -- 6.4.1.1 Register Machine Instruction Format -- 6.4.1.2 Register Machine Programming Example -- 6.4.2 The Register Implicit Machine -- 6.4.2.1 Register Implicit Machine Instruction Format.

6.4.2.2 Register Implicit Machine Program- ming Example -- 6.4.3 The Accumulator Machine -- 6.4.3.1 Accumulator Machine Instruction For- mat -- 6.4.3.2 Accumulator Machine Programming Example -- 6.4.4 The Stack Machine -- 6.4.4.1 Stack Machine Instruction Format -- 6.4.4.2 Stack Machine Programming Example -- 6.5 ISA DESIGN ISSUES -- 6.5.1 Number of Registers -- 6.5.2 Word Size -- 6.5.3 Variable or Fixed-Length Instructions -- 6.5.4 Memory Access -- 6.5.5 Instruction Set Size -- 6.5.5.1 RISC versus CISC Architectures -- 6.5.5.2 Orthogonality and Completeness -- 6.5.6 ISA -- 6.6 THE BRIM MACHINE -- 6.7 SUMMARY -- 6.8 EXERCISES -- Chapter 7 Hardwired CPU Design -- 7.1 REGISTER IMPLICIT MACHINE DESIGN -- 7.1.1 The Data-Path -- 7.1.1.1 Bus-Based Data-Path -- 7.1.1.2 The ALU -- 7.1.1.3 The Mode MUX -- 7.1.2 The RIM Control Unit -- 7.1.2.1 Fetching an Instruction -- 7.1.2.2 Decoding an Instruction -- 7.1.2.3 Executing an Instruction -- 7.1.2.4 The CU Behavioral Description -- 7.1.2.5 The Control Circuitry -- 7.2 CONTROL FOR OTHER ARCHITECTURES -- 7.2.1 Control for the Register Machine -- 7.2.2 Control for the Accumulator Machine -- 7.2.3 Control for the Stack Machine -- 7.3 SUMMARY -- 7.4 EXERCISES -- Chapter 8 Computer Arithmetic -- 8.1 LOGIC AND SHIFT OPERATIONS -- 8.2 ARITHMETIC OPERATIONS -- 8.2.1 Unsigned and Signed Integers -- 8.2.2 Unsigned Arithmetic -- 8.2.2.1 Unsigned Addition -- 8.2.2.2 Unsigned Subtraction -- 8.2.2.3 Unsigned Multiplication -- 8.2.2.4 Unsigned Division -- 8.2.3 Signed Arithmetic -- 8.2.3.1 Signed Addition and Subtraction -- 8.2.3.2 Signed Multiplication and Division -- 8.2.4 Floating-Point Data -- 8.2.4.1 Converting between Floating-Point and Decimal -- 8.2.4.2 Standardization -- 8.2.4.3 Field Order -- 8.2.4.4 Arithmetic Approximation -- 8.2.4.5 Rounding -- 8.2.4.6 Floating-Point Addition.

8.2.4.7 Floating-Point Multiplication -- 8.3 SUMMARY -- 8.3.1 Wallace Trees -- 8.3.2 ROM Lookup Tables -- 8.3.3 Arithmetic Pipelines -- 8.4 EXERCISES -- Chapter 9 Micro-Programmed CPU Design -- 9.1 MICRO-INSTRUCTION FORMAT -- 9.1.1 The Sequence Field -- 9.1.2 The Select and Address Sub elds, and the Ad- dress Selector -- 9.2 MICRO-ARCHITECTURES -- 9.2.1 Direct Control -- 9.2.2 Horizontal Control -- 9.2.3 Vertical Control -- 9.3 MICRO-CONTROL FOR THE BRIM MACHINE -- 9.3.1 The BRIM Micro-Program -- 9.3.2 The BRIM Jump-Table and Mapper -- 9.3.3 The Dec -- 9.4 SUMMARY -- 9.4.1 Ease of Processor Modi cation -- 9.4.2 Complexity of the Processor Circuitry -- 9.4.3 Speed of Machine Instruction Execution -- 9.5 EXERCISES -- Chapter 10 A Few Last Topics -- 10.1 DECREASING EXECUTION TIME -- 10.1.1 Cache Memory -- 10.1.1.1 Direct Mapped Cache -- 10.1.1.2 Writing to Cache -- 10.1.1.3 Cache Performance -- 10.1.2 Instruction Pipelining -- 10.1.2.1 Problems with Pipelines -- 10.1.2.2 Pipeline Performance -- 10.2 INCREASING MEMORY SPACE -- 10.2.1 The Memory Hierarchy -- 10.2.2 Virtual Memory -- 10.2.2.1 Paging -- 10.2.2.2 Page Replacement -- 10.2.2.3 Disk Access -- 10.2.2.4 Memory Protection -- 10.3 SUMMARY -- 10.3.1 I/O Structure -- 10.3.2 Parallel Architectures -- 10.4 EXERCISES -- Suggested Readings -- Index.