Design methodology for RF CMOS phase lock loops

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After a review of PLL essentials, this uniquely comprehensive workbench guide takes you step-by-step through operation principles, design procedures, phase noise analysis, layout considerations, and CMOS realizations for each PLL building block.

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Title Statements

Full title :Design methodology for RF CMOS phase lock loops / Carlos Quemada, Guillermo Bistue, Inigo Adin.

Summary

Edition Statements

Publication Date:©2009.

Publication Statements

Publisher(s):Artech House
Place of Publication:Boston
Language:eng
Publication Date:©2009.

The Physical Object

Description:1 online resource (xii, 226 pages) : : illustrations.

Edition Identifiers

oclc:ocn848043078
LC Classification:TK7872.P38
Dewey Decimal:621.3815/364

Design Methodology for RF CMOS Phase Locked Loops; Contents; Preface; 1 Approach to CMOS PLL Design; 2 PLL Fundamentals; 3 LC-Tank Integrated Oscillators; 4 Frequency Divider; 5 Phase Frequency Detector/Phase Detector; 6 Determination of Building Blocks Specifications; 7 Design of a 3.2-GHz CMOS VCO; 8 Design of a Frequency Divider; 9 Design of a Phase Frequency Detector; 10 Design of the Complete PLL; 11 PLL Characterization and Results; About the Authors; Index