Finite state machine datapath design, optimization, and implementation
Finite State Machine Datapath Design, Optimization, and Implementation explores the design space of combined FSM/Datapath implementations. The lecture starts by examining performance issues in digital systems such as clock skew and its effect on setup and hold time constraints, and the use of pipelining for increasing system clock frequency. This is followed by definitions for latency and throughput, with associated resource tradeoffs explored in detail through the use of dataflow graphs and sc…
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- Full title :Finite state machine datapath design, optimization, and implementation / Justin Davis, Robert Reese.
Summary
Finite State Machine Datapath Design, Optimization, and Implementation explores the design space of combined FSM/Datapath implementations. The lecture starts by examining performance issues in digital systems such as clock skew and its effect on setup and hold time constraints, and the use of pipelining for increasing system clock frequency. This is followed by definitions for latency and throughput, with associated resource tradeoffs explored in detail through the use of dataflow graphs and scheduling tables applied to examples taken from digital signal processing applications. Also, design issues relating to functionality, interfacing, and performance for different types of memories commonly found in ASICs and FPGAs such as FIFOs, single-ports, and dual-ports are examined. Selected design examples are presented in implementation-neutral Verilog code and block diagrams, with associated design files available as downloads for both Altera Quartus and Xilinx Virtex FPGA platforms. A working knowledge of Verilog, logic synthesis, and basic digital design techniques is required. This lecture is suitable as a companion to the synthesis lecture titled Introduction to Logic Synthesis using Verilog HDL.
Read More ↓Edition Statements
- Publication Date:©2008.
Publication Statements
- Publisher(s):Morgan & Claypool Publishers
- Place of Publication:San Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA)
- Language:eng
- Publication Date:©2008.
Notes
Title from PDF title page (viewed on October 11, 2008).
The Physical Object
- Description:1 online resource (123 pages)
Edition Identifiers
- ISBN:1598295306, 9781598295306, 1598295292, 9781598295290
- DOI:10.2200/S00087ED1V01Y200702DCS014
- oclc:on1127178731
- LC Classification:TK7888.3
- Dewey Decimal:621.3916
Table of Contents
Chapter 1. Calculating maximum clock frequency -- Chapter 2. Improving design performance -- Chapter 3. Finite state machine with datapath (FSMD) design -- Chapter 4. Embedded memory usage in finite state machine with datapath (FSMD) designs.
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