Logic synthesis and verification

Logic synthesis and verification

by Hassoun, Soha Sasao, Tsutomu

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Title Statements

  • Full title :Logic synthesis and verification / editors Soha Hassoun, Tsutomu Sasao.

Edition Statements

  • Publication Date:2003, ©2002.
  • Edition:2nd print

Publication Statements

The Physical Object

  • Description:XIV, 454 str. : : ilustr. ; : 24 cm.

Edition Identifiers

  • ISBN:0792376064, 9780792376064
  • oclc:ocn441200332
  • Dewey Decimal:621.39/5

Subjects

CAD Circuitos lógicos Circuits logiques -- Conception assisté… Logic circuits -- Computer-aided design Logic design -- Data processing logična vezja Structure logique -- Informatique

Writers

Hassoun, Soha Sasao, Tsutomu

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