Logic synthesis and verification algorithms

Logic synthesis and verification algorithms

by Hachtel, Gary D.

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Title Statements

  • Full title :Logic synthesis and verification algorithms / by Gary D. Hachtel, Fabio Somenzi.

Edition Statements

  • Publication Date:c1996.

Publication Statements

The Physical Object

  • Description:xxxi, 564 p. : : ill. ; : 26 cm.

Edition Identifiers

  • ISBN:9786610200801, 6610200807, 0792397460, 9780792397465, 0306475928, 9780306475924
  • oclc:on1295503262
  • LC Classification:TK7874.75
  • Dewey Decimal:621.39/5

Subjects

Circuits intégrés -- Vérification Computer-aided design computer-aided designs (visual works) Conception assistée par ordinateur Integrated circuits -- Verification Integrated circuits -- Very large scale… Logic design -- Data processing Structure logique -- Informatique

Writers

Hachtel, Gary D. Somenzi, Fabio

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