Logic synthesis and verification algorithms

Logic synthesis and verification algorithms

by Hachtel, Gary D.

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Title Statements

  • Full title :Logic synthesis and verification algorithms / by Gary D. Hachtel, Fabio Somenzi.

Edition Statements

  • Publication Date:1996.

Publication Statements

  • Publisher(s):Kluwer Academic
  • Place of Publication:Boston
  • Language:eng
  • Publication Date:1996.

The Physical Object

  • Description:XXXI, 564 p. ; : 26 cm

Edition Identifiers

  • ISBN:0792397460, 9780792397465
  • oclc:ocn928103864

Subjects

Circuitos integrados a muy gran escala … Diseño asistido por ordenador Diseño lógico -- Informática

Writers

Hachtel, Gary D. Somenzi, Fabio

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