Logic synthesis and verification algorithms

Logic synthesis and verification algorithms

by Hachtel, Gary D.

Type Book
Rate 0.0 /5
Details
Files
Reviews
Download

Title Statements

  • Full title :Logic synthesis and verification algorithms / by Gary D. Hachtel, Fabio Somenzi.

Edition Statements

  • Publication Date:©2002, 1996.

Publication Statements

  • Publisher(s):Kluwer Academic
  • Place of Publication:Boston
  • Language:eng
  • Publication Date:©2002, 1996.

The Physical Object

  • Description:1 online resource (xxxii, 597 p.) : : illustrations

Edition Identifiers

  • ISBN:0306475928, 9780306475924
  • oclc:ocn937309398
  • LC Classification:TK7874.75

Subjects

Circuits intégrés -- Vérification Computer-aided design computer-aided designs (visual works) Conception assistée par ordinateur Integrated circuits -- Verification Integrated circuits -- Very large scale… Logic design -- Data processing Structure logique -- Informatique

Writers

Hachtel, Gary D. Somenzi, Fabio

Rate & Review

0.0/5
(0 people Voted)

No reviews yet. Be the first to rate this work.

Files & Downloads

No downloadable files are registered for this work yet.

Log in to request a copy