Logic synthesis and verification algorithms

Logic synthesis and verification algorithms

by Hachtel, Gary D.

Type Book
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Title Statements

  • Full title :Logic synthesis and verification algorithms / by Gary D. Hachtel, Fabio Somenzi.

Edition Statements

  • Publication Date:©2002, 1996.

Publication Statements

  • Publisher(s):Kluwer Academic
  • Place of Publication:Boston
  • Language:eng
  • Publication Date:©2002, 1996.

Notes

Titre de l'écran-titre (visionné le 8 août 2011).

TRAITEMENT SOMMAIRE.

The Physical Object

  • Description:1 online resource

Edition Identifiers

  • ISBN:9780306475924, 0306475928
  • oclc:ocn754038090
  • LC Classification:TK7874.75

Table of Contents

Cover -- Table of Contents -- Preface -- Part I Introduction -- Chapter 1 Introduction -- 1.1 VLSI: Opportunity and Challenge -- 1.2 VLSI Processes -- 1.3 Design Styles -- 1.4 Overview of Optimal Logic Synthesis -- 1.5 Graph Algorithms and Complexity -- 1.6 Asymptotic Complexity (or just complexity) -- 1.7 Brief Summary of MOS Device Behavior -- 1.8 Notes -- 1.9 Summary -- 1.10 Problems -- Chapter 2 A Quick Tour of Logic Synthesis with the Help of a Simple Example -- 2.1 A Simple Case Conversion Circuit -- 2.2 First Refinement -- 2.3 The Transform Block -- 2.4 The Command Interpreter -- 2.5 Technology Mapping -- 2.6 Problems -- Part II Two Level Logic Synthesis -- Chapter 3 Boolean Algebras -- 3.1 Sets, Relations, and Functions -- 3.2 Partial Orders -- 3.3 Boolean Functions -- 3.4 Don't Care Conditions as Boolean Function Algebra Intervals -- 3.5 Incomplete Specification of Boolean Functions -- 3.6 Notes -- 3.7 Summary -- 3.8 Problems -- Chapter 4 Synthesis of Two-Level Circuits -- 4.1 Design Optimality -- 4.2 Two-Level Logic -- 4.3 Sums of Products and Products of Sums -- 4.4 Implicants and Prime Implicants -- 4.5 Iterated Consensus -- 4.6 Recursive Computation of Prime Implicant…

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