Logic synthesis and verification algorithms

Logic synthesis and verification algorithms

by Hachtel, Gary D. Somenzi, Fabio

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Title Statements

  • Full title :Logic synthesis and verification algorithms / by Gary D. Hachtel, Fabio Somenzi

Edition Statements

  • Publication Date:©2002, 1996

Publication Statements

  • Publisher(s):Kluwer Academic
  • Place of Publication:Boston
  • Language:eng
  • Publication Date:©2002, 1996

The Physical Object

  • Description:1 online resource (xxxii, 597 p.) : illustrations

Edition Identifiers

  • ISBN:0306475928, 9780306475924, 0792397460, 9780792397465
  • oclc:ocn896926300
  • LC Classification:TK7874.75

Subjects

Circuits intégrés -- Vérification Computer-aided design computer-aided designs (visual works) Conception assistée par ordinateur Integrated circuits -- Verification Integrated circuits -- Very large scale… Logic design -- Data processing Structure logique -- Informatique

Writers

Hachtel, Gary D. Somenzi, Fabio

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