Logic synthesis and verification algorithms

Logic synthesis and verification algorithms

by Hachtel, Gary D.

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Title Statements

  • Full title :Logic synthesis and verification algorithms / by Gary D. Hachtel, Fabio Somenzi.

Edition Statements

  • Publication Date:1998, ©1996.
  • Edition:2nd print., with corrections

Publication Statements

The Physical Object

  • Description:xxxii, 564 pages : : illustrations ; : 26 cm

Edition Identifiers

  • ISBN:0792397460, 9780792397465
  • oclc:ocm39119806
  • LC Classification:TK7874.75
  • Dewey Decimal:621.39/5

Subjects

Circuits intégrés -- Vérification Computer-aided design computer-aided designs (visual works) Conception assistée par ordinateur Conception technique -- Informatique Integrated circuits -- Verification Integrated circuits -- Very large scale… Logic design -- Data processing Logique informatique -- Circuits intégr… Structure logique -- Informatique

Writers

Hachtel, Gary D. Somenzi, Fabio

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