On-chip networks

by Enright Jerger, Natalie D.

Type Book

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Title Statements

Full title :On-chip networks / Natalie Enright Jerger, Tushar Krishna, Li-Shiuan Peh.

Summary

This book targets engineers and researchers familiar with basic computer architecture concepts who are interested in learning about on-chip networks. This work is designed to be a short synthesis of the most critical concepts in on-chip network design. It is a resource for both understanding on-chip network basics and for providing an overview of state of-the-art research in on-chip networks. We believe that an overview that teaches both fundamental concepts and highlights state-of-the-art designs will be of great value to both graduate students and industry engineers. While not an exhaustive text, we hope to illuminate fundamental concepts for the reader as well as identify trends and gaps in on-chip network research. With the rapid advances in this field, we felt it was timely to update and review the state of the art in this second edition. We introduce two new chapters at the end of the book. We have updated the latest research of the past years throughout the book and also expanded our coverage of fundamental concepts to include several research ideas that have now made their way into products and, in our opinion, should be textbook concepts that all on-chip network practitioners should know. For example, these fundamental concepts include message passing, multicast routing, and bubble flow control schemes.

Edition Statements

Publication Date:2017.
Edition:Second edition

Publication Statements

Publisher(s):Morgan & Claypool
Place of Publication:San Rafael, California
Language:eng
Publication Date:2017.

Notes

Part of: Synthesis digital library of engineering and computer science.

The Physical Object

Description:1 ressource en ligne (xix, 190 pages) : : illustrations

Edition Identifiers

ISBN:9781627059961, 1627059962
oclc:on1027975177
LC Classification:TK5105.546
Dewey Decimal:004.1

1. Introduction -- 1.1 The advent of the multi-core era -- 1.1.1 Communication demands of multi-core architectures -- 1.2 On-chip vs. off-chip networks -- 1.3 Network basics: a quick primer -- 1.3.1 Evolution to on-chip networks -- 1.3.2 On-chip network building blocks -- 1.3.3 Performance and cost -- 1.4 This book, second edition

2. Interface with system architecture -- 2.1 Shared memory networks in chip multiprocessors -- 2.1.1 Impact of coherence protocol on network performance -- 2.1.2 Coherence protocol requirements for the on-chip network -- 2.1.3 Protocol-level network deadlock -- 2.1.4 Impact of cache hierarchy implementation on network performance -- 2.1.5 Home node and memory controller design issues -- 2.1.6 Miss and transaction status holding registers -- 2.1.7 Brief state-of-the-art survey -- 2.2 Message passing -- 2.2.1 Brief state-of-the-art survey -- 2.3 NoC interface standards -- 2.4 Conclusion

3. Topology -- 3.1 Metrics -- 3.1.1 Traffic-independent metrics -- 3.1.2 Traffic-dependent metrics -- 3.2 Direct topologies: rings, meshes, and Tori -- 3.3 Indirect topologies: crossbars, butterflies, Clos networks, and fat trees -- 3.4 Irregular topologies -- 3.4.1 Split…