CD-ROM contains: WaveFormer Pro (interactive HDL simulator, timing diagram editor, VHDL, Verilog, & SPICE stimulus generator) -- VeriLogger Pro (Verilog simulator with unit level test environment) -- TestBencher Pro (generates reactive VHDL and Verilog test benches from timing d…
Presenting a methodology for using domino logic in an ASIC design flow developed over several years in an industrial context, this text covers practical issues related to the use of domino logic in an automated framework, and brings together all the knowledge needed to apply the…
Communication Complexity describes a new intuitive model for studying circuit networks that captures the essence of circuit depth. Although the complexity of boolean functions has been studied for almost 4 decades, the main problems the inability to show a separation of any two …