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We propose a novel approach to the analysis and design of reliable power distribution networks for digital VLSI circuits. The optimized power and ground buses should meet or outperform the noise level specifications while achieving minimum die size. The flow consists of two main…
Increasing levels of VLSI integration present new opportunities, and new challenges, for designers of high performance microprocessor-based systems. With more transistors at their disposal, architects are faced with complex decisions regarding processor features, cache hierarchi…
Wireless sensor networks have the potential to impact society through applications from environmental and health monitoring, to military surveillance. Network nodes are designed for extremely long lifetimes, and often rely on energy harvesting or scavenging devices for power, as…
Multi-carrier digital subscriber line (DSL) systems, such as asymmetric DSL (ADSL) and very high data rate DSL (VDSL), are typically constrained by crosstalk interference. Recent advances in suppression of in-domain far-end crosstalk (self-FEXT) have allowed these systems to ach…
The introduction of turbo codes in 1993 was a major milestone in coding theory that had spurred a renaissance in iterative decoding, leading to breakthroughs in performance over maximum likelihood decoding. Since then, the works of Gallager in 1963 on low-density parity-check (L…
While improving circuit's speed and reducing its area have been the primary figure of merits in digital VLSI design, more efforts are now spent on minimizing power dissipation. This is becoming equally true for both high-performance chips, such as microprocessors, to reduce cool…
A physically based, 3-dimensional geometry independent model for profile evolution in low pressure deposition and etching processes has been developed. The model has been used to simulate a variety of low pressure deposition and etching processes such as low pressure chemical va…
Several yield and reliability enhancement techniques have been proposed for the compaction, routing and technology mapping stages of VLSI design. For yield, we modify the existing layouts to reduce the sensitivity of the design to random point defects, which are the main yield d…
With the increase of circuit size and complexity, logic design errors can occur. Logic design errors are functional mismatches between the specification and gate-level implementation. Once a verification tool has found that the design is erroneous, logic debugging must be perfor…
As CMOS scaling moves towards the end of technology road map, a plethora of reliability issues are emerging as challenging obstacles for designing a stable/robust circuit system. Reliability issues in nano-scale designs can be broadly categorized into spatial and temporal compon…