Logic synthesis and verification algorithms

Logic synthesis and verification algorithms

by Hachtel, Gary D.

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Title Statements

  • Full title :Logic synthesis and verification algorithms / by Gary D. Hachtel, Fabio Somenzi.

Edition Statements

  • Publication Date:2002.

Publication Statements

The Physical Object

  • Description:1 online resource

Edition Identifiers

  • ISBN:0306475928, 9780306475924, 0792397460, 9780792397465
  • oclc:ocn803628642

Subjects

Circuits integrats -- Verificació Circuits integrats -- VLSI Circuits integrats a molt gran escala Disseny assistit per ordinador Disseny lògic -- Processament de dades Estructura lògica Llibres electrònics

Writers

Hachtel, Gary D. Somenzi, Fabio

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