Verification by error modeling: using testing techniques in hardware verification

Title Statements

• Full title :Verification by error modeling : using testing techniques in hardware verification / written by Katarzyna Radecka, Zeljko Zilic.

Edition Statements

• Publication Date:2003.

Publication Statements

• Publisher(s):Kluwer Academic Publishers
• Place of Publication:Boston
• Language:eng
• Publication Date:2003.

The Physical Object

• Description:1 online resource

Edition Identifiers

• ISBN:030648739X, 9780306487392, 1402076525, 9781402076527
• oclc:ocn803684170

Subjects

Writers

More from this Series

• Fault injection techniques and tools for embedded systems reliability…

  ©2003.

  more →

• Fault injection techniques and tools for embedded systems reliability…

  2003.

  more →

  

• Fault injection techniques and tools for embedded systems reliability…

  ©2004.

  more →

  

• Fault injection techniques and tools for embedded systems reliability…

  ©2003.

  more →

  

• Fault injection techniques and tools for embedded systems reliability…

  ©2003

  more →