Logic synthesis and verification algorithms

Logic synthesis and verification algorithms

by Hachtel, Gary D.

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Title Statements

  • Full title :Logic synthesis and verification algorithms / by Gary D. Hachtel ; Fabio Somenzi.

Edition Statements

  • Publication Date:2000.

Publication Statements

  • Publisher(s):Kluwer Acad. Publ
  • Place of Publication:Boston
  • Language:eng
  • Publication Date:2000.

Notes

Literaturverz. S. 537 - 553.

The Physical Object

  • Description:XXXI, 564 Seiten : : Diagramme ; : 26 cm

Edition Identifiers

  • ISBN:0792397460, 9780792397465
  • oclc:ocn250040542
  • LC Classification:TK7874.75
  • Dewey Decimal:621.39/5

Subjects

Computer-aided design Entwurfsautomation ; SWD-ID: 43125360 Integrated circuits Logic design Logiksynthese Logischer Entwurf

Writers

Hachtel, Gary D. Somenzi, Fabio

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