Thesiss

In this thesis we present new methods that contribute to higher fault coverage and shorter test time for testing bridging faults in VLSI circuits. We present a hierarchical bridging fault extraction method which has same degree of accuracy as a flat extractor. In addition, it is…

High-performance CPUs commonly deployed in data-centers accumulate a significant amount of energy and run in the millions of kilowatts per year. This family of CPUs can highly benefit from low power techniques that do not negatively impact performance. This work addresses the is…

With the increase of circuit size and complexity, logic design errors can occur. Logic design errors are functional mismatches between the specification and gate-level implementation. Once a verification tool has found that the design is erroneous, logic debugging must be perfor…