Digital logic design using Verilog

Digital logic design using Verilog: coding and RTL synthesis

by Taraate, Vaibbhav

Type Book
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This second edition focuses on the thought process of digital design and implementation in the context of VLSI and system design. It covers the Verilog 2001 and Verilog 2005 RTL design styles, constructs and the optimization at the RTL and synthesis level. The book also covers the logic synthesis, low power, multiple clock domain design concepts and design performance improvement techniques. The book includes 250 design examples/illustrations and 100 exercise questions. This volume can be used …

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Title Statements

  • Full title :Digital logic design using Verilog : coding and RTL synthesis / Vaibbhav Taraate.

Summary

This second edition focuses on the thought process of digital design and implementation in the context of VLSI and system design. It covers the Verilog 2001 and Verilog 2005 RTL design styles, constructs and the optimization at the RTL and synthesis level. The book also covers the logic synthesis, low power, multiple clock domain design concepts and design performance improvement techniques. The book includes 250 design examples/illustrations and 100 exercise questions. This volume can be used as a core or supplementary text in undergraduate courses on logic design and as a text for professional and vocational coursework. In addition, it will be a hands-on professional reference and a self-study aid for hobbyists.

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Edition Statements

  • Publication Date:©2022
  • Edition:Second edition

Publication Statements

  • Publisher(s):Springer
  • Place of Publication:Singapore
  • Language:eng
  • Publication Date:©2022

The Physical Object

  • Description:1 online resource : : illustrations (chiefly color)

Edition Identifiers

  • ISBN:9789811631993, 9811631999
  • DOI:10.1007/978-981-16-3199-3
  • oclc:on1282597525
  • LC Classification:TK7868.L6
  • Dewey Decimal:621.39/5

Table of Contents

Introduction -- Combinational Logic Design (Part I) -- Combinational Logic Design (Part II) -- Combinational Design Guidelines -- Sequential Logic Design -- Sequential Design Guidelines -- Complex Designs using Verilog RTL -- Finite State Machines -- Simulation Concepts and PLD Based Designs -- RTL Synthesis -- Static Timing Analysis (STA) -- Constraining Design -- Multiple Clock Domain Designs -- Low Power Design -- RTL Design for SOCs.

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Subjects

Logic design -- Data processing Structure logique -- Informatique Verilog (Computer hardware description … Verilog (Langage de description de maté…

Writers

Taraate, Vaibbhav

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