Synchronous precharge logic

by Smoszna, Marek

Type Book

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Title Statements

Full title :Synchronous precharge logic / Marek Smoszna.

Summary

Precharge logic is used by a variety of industries in applications where processor speed is the primary goal, such as VLSI (very large systems integration) applications. Also called dynamic logic, this type of design uses a clock to synchronize instructions in circuits. This comprehensive book covers the challenges faced by designers when using this logic style, including logic basics, timing, noise considerations, alternative topologies and more. In addition advanced topics such as skew tolerant design are covered in some detail. Overall this is a comprehensive view of precharge logic, which should be useful to graduate students and designers in the field alike. It might also be considered as a supplemental title for courses covering VLSI. Comprehensive guide to precharge logic. Explains both the advantages and disadvantages to help engineers decide when to utilize precharge logic. Useful for engineers in a variety of industries.

Edition Statements

Publication Date:2012.

Publication Statements

Publisher(s):Elsevier
Place of Publication:Place of publication not identified
Language:eng
Publication Date:2012.

The Physical Object

Description:1 online resource

Edition Identifiers

ISBN:9780123985279, 0123985277, 1283526697, 9781283526692, 9780124017078, 012401707X
oclc:ocn802363762
LC Classification:TK7868.L6
Dewey Decimal:621.39/5

Front Cover; Synchronous Precharge Logic; Copyright Page; Dedication; Contents; List of figures; List of tables; About the author; 1 Precharge Logic Basics; 1.1 Introduction; 1.2 What Is Precharge Logic?; 1.3 Why Is it Faster than Static Logic?; 1.4 Advantages of Precharge Logic; 1.5 What About Using Other Transistors?; 1.6 Domino Logic; 1.6.1 Need for Monotonic Signals; 1.6.2 Domino Logic Gates; 1.7 Keepers: Improving the Charge Storage; 1.8 Final Comments; 2 Timing; 2.1 Clock Skew Penalty; 2.2 Hold-Time Problem; 2.3 Nonoverlapping Clocks; 2.4 A Better Latch; 2.5 Input Setup Criteria.

2.6 Input Hold Criteria2.7 Precharge Timing; 2.8 Skew Tolerant Design; 3 Transistor Sizing; 3.1 Sizing the Pulldown Stack; 3.2 Sizing of the Output Inverter; 3.3 Logical Effort; 3.4 Sizing of the Keeper Device; 3.4.1 PFET Keeper; 3.4.2 NFET Keeper; 3.4.3 Maximum Leakable NFET Width; 3.5 Sizing of the Precharge Device; 3.6 Sizing Precharge Gates with Wires; 4 Noise Tolerance; 4.1 Input-Connected Prechargers; 4.2 Propagated Noise; 4.3 Input Wire Noise; 4.4 Supply-Level Variations; 4.5 Charge Sharing; 4.6 Charge Sharing: Example 1; 4.7 Charge Sharing: Example 2; 4.8 Leakage.

4.9 Clock Coupling on the…